1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to apparatus in the central processing unit that performs the manipulation of the data signal groups determined by the instruction sequence generally referred to as floating point operations.
2. Description of the Related Art
In the modern data processing system, groups of data signals can be chosen to represent the sign (+), the fraction or numeric value (A,B), and the position of the binary point of a numeric value (E.sub.A, E.sub.B). This representation is referred to as a floating point representation of a numeric quantity. (According to convention, the floating point fraction field is normalized to provide a non-zero quantity in the most significant bit position of the fraction field.) The floating point representation of a numeric quantity has the advantage that a wide range of values can be accommodated with the same degree of accuracy. However, the manipulation of the floating point quantities, because of the structure of the representation of a number, is slower than manipulation of the typical representation of numeric quantities in which the binary point has a predefined location.
Referring to FIG. 1, the selected components of a typical data processing system are shown. The data processing system generally includes a central processing unit 10 wherein the manipulation of data signal groups according to instruction sequences or programs are performed, a main memory unit 12 wherein the software programs (and associated tables) utilized by the central processing unit is stored, and at least one interface unit 11 that provides secondary storage for data and program signal groups and permits communication by the central processing unit with external devices. The central processing unit 10 includes an instruction unit 13 that responds to instruction signal groups by enabling predetermined apparatus in the proper sequence for performing the activity defined by the instruction. In particular, the instruction unit 13 controls the execution unit 14 which performs the operations, on data signal groups applied thereto, defined by the instruction signal groups. In the execution unit 14, an arithmetic unit 15 typically performs the arithmetic operations defined by the instruction signal group. Where feasible, a separate floating point arithmetic unit 16 is included. A separate floating point arithmetic unit is utilized because the floating point arithmetic operation execution time is relatively lengthy and requires special circuit configurations. The present invention relates to the floating point arithmetic unit.